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P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core 8 kb flash with 512-byte data eeprom and 768-byte ram rev. 04 06 january 2004 product data 1. general description the P89LPC932 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80c51 devices. many system-level functions have been incorporated into the P89LPC932 in order to reduce component count, board space, and system cost. 2. features n a high performance 80c51 cpu provides instruction cycle times of 167-333 ns for all instructions except multiply and divide when executing at 12 mhz. this is 6 times the performance of the standard 80c51 running at the same clock frequency. a lower clock frequency for the same performance results in power savings and reduced emi. n 2.4 v to 3.6 v v dd operating range. i/o pins are 5 v tolerant (may be pulled up or driven to 5.5 v). n 8 kb flash code memory with 1 kb erasable sectors, 64-byte erasable page size. n 256-byte ram data memory. 512-byte auxiliary on-chip ram. n 512-byte customer data eeprom on chip allows serialization of devices, storage of set-up parameters, etc. n two 16-bit counter/timers. each timer may be con?gured to toggle a port output upon timer over?ow or to become a pwm output. n real-time clock that can also be used as a system timer. n capture/compare unit (ccu) provides pwm, input capture, and output compare functions. n two analog comparators with selectable inputs and reference source. n enhanced uart with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities. n 400 khz byte-wide i 2 c-bus communication port. n spi communication port. n eight keypad interrupt inputs, plus two additional external interrupt inputs. n four interrupt priority levels. n watchdog timer with separate on-chip oscillator, requiring no external components. the watchdog prescaler is selectable from 8 values. n active-low reset. on-chip power-on reset allows operation without external reset components. a reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. a software reset function is also available. n low voltage reset (brownout detect) allows a graceful system shutdown when power fails. may optionally be con?gured as an interrupt.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 2 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. n oscillator fail detect. the watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. n con?gurable on-chip oscillator with frequency range and rc oscillator options (selected by user programmed flash con?guration bits). the rc oscillator option allows operation without external oscillator components. oscillator options support frequencies from 20 khz to the maximum operating frequency of 12 mhz. the rc oscillator option is selectable and ?ne tunable. n programmable port output con?guration options: u quasi-bidirectional, u open drain, u push-pull, u input-only. n port input pattern match detect. port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. n second data pointer. n schmitt trigger port inputs. n led drive capability (20 ma) on all port pins. a maximum limit is speci?ed for the entire chip. n controlled slew rate port outputs to reduce emi. outputs have approximately 10 ns minimum ramp times. n 23 i/o pins minimum (28-pin package). up to 26 i/o pins while using on-chip oscillator and reset options. n only power and ground connections are required to operate the P89LPC932 when on-chip oscillator and reset options are selected. n serial flash programming allows simple in-circuit production coding. flash security bits prevent reading of sensitive application programs. n in-application programming of the flash code memory. this allows changing the code in a running application. n idle and two different power-down reduced power modes. improved wake-up from power-down mode (a low interrupt input starts execution). typical power-down current is 1 m a (total power-down with voltage comparators disabled). n 28-pin plcc, tssop, and hvqfn packages. n emulation support.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 3 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3. ordering information 3.1 ordering options table 1: ordering information type number package name description version P89LPC932ba plcc28 plastic leaded chip carrier; 28 leads sot261-2 P89LPC932bdh tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 P89LPC932fdh tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 P89LPC932fhn hvqfn28 plastic thermal enhanced very thin quad ?at package; no leads; 28 terminals; body 6 6 0.85 mm sot788-1 table 2: part options type number flash memory temperature range frequency P89LPC932ba 8 kb 0 cto+70 c 0 to 12 mhz P89LPC932bdh 8 kb 0 cto+70 c 0 to 12 mhz P89LPC932fdh 8 kb - 40 cto+85 c 0 to 12 mhz P89LPC932fhn 8 kb - 40 cto+85 c 0 to 12 mhz
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 4 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4. block diagram fig 1. block diagram. high performance accelerated 2-clock 80c51 cpu 8 kb code flash 256-byte data ram port 2 configurable i/os port 1 configurable i/os port 0 configurable i/os keypad interrupt programmable oscillator divider cpu clock configurable oscillator on-chip rc oscillator internal bus crystal or resonator power monitor (power-on reset, brownout reset) 002aaa510 uart real-time clock/ system timer spi timer 0 timer 1 watchdog timer and oscillator analog comparators 512-byte auxiliary ram i 2 c 512-byte data eeprom port 3 configurable i/os ccu (capture/ compare unit) P89LPC932
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 5 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. pinning information 5.1 pinning fig 2. tssop28 pin con?guration. handbook, halfpage P89LPC932bdh P89LPC932fdh 002aaa512 1 2 3 4 5 6 7 8 9 10 11 12 13 14 icb/p2.0 ocd/p2.1 kbi0/cmp2/p0.0 occ/p1.7 ocb/p1.6 rst/p1.5 v ss xtal1/p3.1 clkout/xtal2/p3.0 int1/p1.4 sda/int0/p1.3 scl/t0/p1.2 mosi/p2.2 miso/p2.3 p2.7/ica p2.6/oca p0.1/cin2b/kbi1 p0.2/cin2a/kbi2 p0.3/cin1b/kbi3 p0.4/cin1a/kbi4 p0.5/cmpref/kbi5 v dd p0.6/cmp1/kbi6 p0.7/t1/kbi7 p1.0/txd p1.1/rxd p2.5/spiclk p2.4/ss 28 27 26 25 24 23 22 21 20 19 18 17 16 15
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 6 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 3. plcc28 pin con?guration. fig 4. hvqfn28 pin con?guration. i dth P89LPC932ba 002aaa513 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 4 3 2 1 28 27 26 p1.7/occ p0.0/cmp2/kbi0 p2.1/ocd p2.0/icb p2.7/ica p2.6/oca p0.1/cin2b/kbi1 scl/t0/p1.2 mosi/p2.2 miso/p2.3 ss/p2.4 spiclk/p2.5 rxd/p1.1 txd/p1.0 ocb/p1.6 rst/p1.5 v ss xtal1/p3.1 clkout/xtal2/p3.0 int1/p1.4 sda/int0/p1.3 p0.2/cin2a/kbi2 p0.3/cin1b/kbi3 p0.4/cin1a/kbi4 p0.5/cmpref/kbi5 v dd p0.6/cmp1/kbi6 p0.7/t1/kbi7 P89LPC932fhn 002aaa514 int1/p1.4 sda/int0/p1.3 clkout/xtal2/p3.0 xtal1/p3.1 v ss rst/p1.5 ocb/p1.6 2 1 3 4 5 6 7 p1.2/t0/scl p2.5/spiclk p2.3/miso p2.4/ss p2.2/mosi p1.1/rxd p1.0/txd 13 11 14 12 10 9 8 icb/p2.0 kbi0/cmp2/p0.0 ocd/p2.1 occ/p1.7 ica/p2.7 kbi1/cin2b/p0.1 oca/p2.6 22 25 23 24 26 27 28 p0.6/cmp1/kbi6 p0.7/t1/kbi7 p0.5/cmpref/kbi5 v dd p0.4/cin1a/kbi4 p0.3/cin1b/kbi3 p0.2/cin2a/kbi2 21 19 20 18 17 16 15
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 7 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5.2 pin description table 3: pin description symbol pin type description tssop, plcc hvqfn p0.0 - p0.7 3, 26, 25, 24, 23, 22, 20, 19 27, 22, 21, 20, 19, 18, 16, 15 i/o port 0: port 0 is an 8-bit i/o port with a user-con?gurable output type. during reset port 0 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 8.12.1 port con?gurations and table 8 dc electrical characteristics for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt triggered inputs. port 0 also provides various special functions as described below: 3 27 i/o p0.0 port 0 bit 0. o cmp2 comparator 2 output. i kbi0 keyboard input 0. 26 22 i/o p0.1 port 0 bit 1. i cin2b comparator 2 positive input b. i kbi1 keyboard input 1. 25 21 i/o p0.2 port 0 bit 2. i cin2a comparator 2 positive input a. i kbi2 keyboard input 2. 24 20 i/o p0.3 port 0 bit 3. i cin1b comparator 1 positive input b. i kbi3 keyboard input 3. 23 19 i/o p0.4 port 0 bit 4. i cin1a comparator 1 positive input a. i kbi4 keyboard input 4. 22 18 i/o p0.5 port 0 bit 5. i cmpref comparator reference (negative) input. i kbi5 keyboard input 5. 20 16 i/o p0.6 port 0 bit 6. o cmp1 comparator 1 output. i kbi6 keyboard input 6. 19 15 i/o p0.7 port 0 bit 7. i/o t1 timer/counter 1 external count input or over?ow output. i kbi7 keyboard input 7.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 8 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. p1.0 - p1.7 18, 17, 12, 11, 10, 6, 5, 4 14, 13, 8, 7, 6, 2, 1, 28 i/o, i [1] port 1: port 1 is an 8-bit i/o port with a user-con?gurable output type, except for three pins as noted below. during reset port 1 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of the con?gurable port 1 pins as inputs and outputs depends upon the port con?guration selected. each of the con?gurable port pins are programmed independently. refer to section 8.12.1 port con?gurations and table 8 dc electrical characteristics for details. p1.2 - p1.3 are open drain when used as outputs. p1.5 is input only. all pins have schmitt triggered inputs. port 1 also provides various special functions as described below: 18 14 i/o p1.0 port 1 bit 0. o txd transmitter output for the serial port. 17 13 i/o p1.1 port 1 bit 1. i rxd receiver input for the serial port. 12 8 i/o p1.2 port 1 bit 2 (open-drain when used as output). i/o t0 timer/counter 0 external count input or over?ow output (open-drain when used as output). i/o scl i 2 c serial clock input/output. 11 7 i/o p1.3 port 1 bit 3 (open-drain when used as output). i int0 external interrupt 0 input. i/o sda i 2 c serial data input/output. 10 6 i p1.4 port 1 bit 4. i int1 external interrupt 1 input. 62 i p1.5 port 1 bit 5 (input only). i rst external reset input during power-on or if selected via ucfg1. when functioning as a reset input, a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. also used during a power-on sequence to force in-system programming mode. 5 1 i/o p1.6 port 1 bit 6. o ocb output compare b. 4 28 i/o p1.7 port 1 bit 7. o occ output compare c. table 3: pin description continued symbol pin type description tssop, plcc hvqfn
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 9 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. p2.0 - p2.7 1, 2, 13, 14, 15, 16, 27, 28 25, 26, 9, 10, 11, 12, 23, 24 i/o port 2: port 2 is an 8-bit i/o port with a user-con?gurable output type. during reset port 2 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 2 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 8.12.1 port con?gurations and table 8 dc electrical characteristics for details. all pins have schmitt triggered inputs. port 2 also provides various special functions as described below: 1 25 i/o p2.0 port 2 bit 0. i icb input capture b. 2 26 i/o p2.1 port 2 bit 1. o ocd output compare d. 13 9 i/o p2.2 port 2 bit 2. i/o mosi spi master out slave in. when con?gured as master, this pin is output; when con?gured as slave, this pin is input. 14 10 i/o p2.3 port 2 bit 3. i/o miso when con?gured as master, this pin is input, when con?gured as slave, this pin is output. 15 11 i/o p2.4 port 2 bit 4. i ss spi slave select. 16 12 i/o p2.5 port 2 bit 5. i/o spiclk spi clock. when con?gured as master, this pin is output; when con?gured as slave, this pin is input. 27 23 i/o p2.6 port 2 bit 6. o oca output compare a. 28 24 i/o p2.7 port 2 bit 7. i ica input capture a. table 3: pin description continued symbol pin type description tssop, plcc hvqfn
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 10 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] input/output for p1.0-p1.4, p1.6, p1.7. input for p1.5. p3.0 - p3.1 9, 8 5, 4 i/o port 3: port 3 is a 2-bit i/o port with a user-con?gurable output type. during reset port 3 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 3 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 8.12.1 port con?gurations and table 8 dc electrical characteristics for details. all pins have schmitt triggered inputs. port 3 also provides various special functions as described below: 9 5 i/o p3.0 port 3 bit 0. o xtal2 output from the oscillator ampli?er (when a crystal oscillator option is selected via the flash con?guration. o clkout cpu clock divided by 2 when enabled via sfr bit (enclk - trim.6). it can be used if the cpu clock is the internal rc oscillator, watchdog oscillator or external clock input, except when xtal1/xtal2 are used to generate clock source for the real-time clock/system timer. 8 4 i/o p3.1 port 3 bit 1. i xtal1 input to the oscillator circuit and internal clock generator circuits (when selected via the flash con?guration). it can be a port pin if internal rc oscillator or watchdog oscillator is used as the cpu clock source, and if xtal1/xtal2 are not used to generate the clock for the real-time clock/system timer. v ss 73 i ground: 0 v reference. v dd 21 17 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 3: pin description continued symbol pin type description tssop, plcc hvqfn
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 11 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. logic symbol 7. special function registers remark: special function registers (sfrs) accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not de?ned. ? accesses to any de?ned sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled -, 0 or 1 can only be written and read as follows: C - unless otherwise speci?ed, must be written with 0, but can return any value when read (even if it was written with 0). it is a reserved bit and may be used in future derivatives. C 0 must be written with 0, and will return a 0 when read. C 1 must be written with 1, and will return a 1 when read. fig 5. logic symbol. v dd v ss P89LPC932 port 0 port 3 port 1 txd rxd t0 int0 int1 rst scl sda 002aaa511 cmp2 cin2b cin2a cin1b cin1a cmpref cmp1 t1 xtal2 xtal1 kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 kbi6 kbi7 clkout ocb occ port 2 icb ocd mosi miso ss spiclk oca ica
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 06 january 2004 12 of 60 table 4: special function registers * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 00000000 auxr1 auxiliary function register a2h clklp ebrr ent1 ent0 srst 0 - dps 00 000000x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 00000000 brgr0 [2] baud rate generator rate low beh 00 00000000 brgr1 [2] baud rate generator rate high bfh 00 00000000 brgcon baud rate generator control bdh - - - - - - sbrgs brgen 00 [2] xxxxxx00 cccra capture compare a control register eah iceca2 iceca1 iceca0 icesa icnfa fcoa ocma1 ocma0 00 00000000 cccrb capture compare b control register ebh icecb2 icecb1 icecb0 icesb icnfb fcob ocmb1 ocmb0 00 00000000 cccrc capture compare c control register ech - - - - - fcoc ocmc1 ocmc0 00 xxxxx000 cccrd capture compare d control register edh - - - - - fcod ocmd1 ocmd0 00 xxxxx000 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 oe1 co1 cmf1 00 [1] xx000000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [1] xx000000 deecon data eeprom control register f1h eeif hverr ectl1 ectl0 - - - eadr8 0e 00001110 deedat data eeprom data register f2h 00 00000000 deeadr data eeprom address register f3h 00 00000000 divm cpu clock divide-by-m control 95h 00 00000000 dptr data pointer (2 bytes) dph data pointer high 83h 00 00000000 dpl data pointer low 82h 00 00000000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 06 january 2004 13 of 60 i2adr i 2 c slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 00000000 bit address df de dd dc db da d9 d8 i2con* i 2 c control register d8h - i2en sta sto si aa - crsel 00 x00000x0 i2dat i 2 c data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 00000000 i2scll serial clock generator/scl duty cycle register low dch 00 00000000 i2stat i 2 c status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 11111000 icrah input capture a register high abh 00 00000000 icral input capture a register low aah 00 00000000 icrbh input capture b register high afh 00 00000000 icrbl input capture b register low aeh 00 00000000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 00000000 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h eiee est - eccu espi ec ekbi ei2c 00 [1] 00x00000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [1] x0000000 ip0h interrupt priority 0 high b7h - pwdrt h pboh psh/ psrh pt1h px1h pt0h px0h 00 [1] x0000000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h piee pst - pccu pspi pc pkbi pi2c 00 [1] 00x00000 ip1h interrupt priority 1 high f7h pieeh psth - pccuh pspih pch pkbih pi2ch 00 [1] 00x00000 kbcon keypad control register 94h - - - - - - patn _sel kbif 00 [1] xxxxxx00 kbmask keypad interrupt mask register 86h 00 00000000 kbpatn keypad pattern register 93h ff 11111111 table 4: special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 06 january 2004 14 of 60 ocrah output compare a register high efh 00 00000000 ocral output compare a register low eeh 00 00000000 ocrbh output compare b register high fbh 00 00000000 ocrbl output compare b register low fah 00 00000000 ocrch output compare c register high fdh 00 00000000 ocrcl output compare c register low fch 00 00000000 ocrdh output compare d register high ffh 00 00000000 ocrdl output compare d register low feh 00 00000000 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h t1/kb7 cmp1 /kb6 cmpref /kb5 cin1a /kb4 cin1b /kb3 cin2a /kb2 cin2b /kb1 cmp2 /kb0 [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h occ ocb rst int1 int0/ sda t0/scl rxd txd [1] bit address 97 96 95 94 93 92 91 90 p2* port 2 a0h ica oca spiclk ss miso mosi ocd icb [1] bit address b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h - - - - - - xtal1 xtal2 [1] p0m1 port 0 output mode 1 84h (p0m1.7) (p0m1.6) (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) (p0m1.0) ff [1] 11111111 p0m2 port 0 output mode 2 85h (p0m2.7) (p0m2.6) (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) (p0m2.0) 00 [1] 00000000 p1m1 port 1 output mode 1 91h (p1m1.7) (p1m1.6) - (p1m1.4) (p1m1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [1] 11x1xx11 p1m2 port 1 output mode 2 92h (p1m2.7) (p1m2.6) - (p1m2.4) (p1m2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [1] 00x0xx00 table 4: special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 06 january 2004 15 of 60 p2m1 port 2 output mode 1 a4h (p2m1.7) (p2m1.6) (p2m1.5) (p2m1.4) (p2m1.3) (p2m1.2) (p2m1.1) (p2m1.0) ff [1] 11111111 p2m2 port 2 output mode 2 a5h (p2m2.7) (p2m2.6) (p2m2.5) (p2m2.4) (p2m2.3) (p2m2.2) (p2m2.1) (p2m2.0) 00 [1] 00000000 p3m1 port 3 output mode 1 b1h - - - - - - (p3m1.1) (p3m1.0) 03 [1] xxxxxx11 p3m2 port 3 output mode 2 b2h - - - - - - (p3m2.1) (p3m2.0) 00 [1] xxxxxx00 pcon power control register 87h smod1 smod0 bopd boi gf1 gf0 pmod1 pmod0 00 00000000 pcona power control register a b5h rtcpd deepd vcpd - i2pd sppd spd ccupd 00 [1] 00000000 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 00000000 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00000x rstsrc reset source register dfh - - bof pof r_bk r_wd r_sf r_ex [3] rtccon real-time clock control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [1][6] 011xxx00 rtch real-time clock register high d2h 00 [6] 00000000 rtcl real-time clock register low d3h 00 [6] 00000000 saddr serial port address register a9h 00 00000000 saden serial port address enable b9h 00 00000000 sbuf serial port data buffer register 99h xx xxxxxxxx bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 00000000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 00000000 sp stack pointer 81h 07 00000111 spctl spi control register e2h ssig spen dord mstr cpol cpha spr1 spr0 04 00000100 spstat spi status register e1h spif wcol - - - - - - 00 00xxxxxx spdat spi data register e3h 00 00000000 tamod timer 0 and 1 auxiliary mode 8fh - - - t1m2 - - - t0m2 00 xxx0xxx0 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 00000000 tcr20* ccu control register 0 c8h pllen hltrn hlten altcd altab tdir2 tmod21 tmod20 00 00000000 tcr21 ccu control register 1 f9h tcou2 - - - plldv.3 plldv.2 plldv.1 plldv.0 00 0xxx0000 table 4: special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 06 january 2004 16 of 60 [1] all ports are in input only (high impedance) state after power-up. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is 0. if any are written while brgen = 1, the result is unpredic table. [3] the rstsrc register re?ects the cause of the P89LPC932 reset. upon a power-up reset, all reset source ?ags are cleared excep t pof and bof; the power-on reset value is xx110000. [4] after reset, the value is 111001x1, i.e., pre2-pre0 are all 1, wdrun = 1 and wdclk = 1. wdtof bit is 1 after watchdog reset and is 0 after power-on reset. other resets will not affect wdtof. [5] on power-on reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initializatio n of the trim register. [6] the only reset source that affects these sfrs is power-on reset. th0 timer 0 high 8ch 00 00000000 th1 timer 1 high 8dh 00 00000000 th2 ccu timer high cdh 00 00000000 ticr2 ccu interrupt control register c9h toie2 tocie2d tocie2c tocie2b tocie2a - ticie2b ticie2a 00 00000x00 tifr2 ccu interrupt ?ag register e9h toif2 tocf2d tocf2c tocf2b tocf2a - ticf2b ticf2a 00 00000x00 tise2 ccu interrupt status encode register deh - - - - - encint. 2 encint. 1 encint. 0 00 xxxxx000 tl0 timer 0 low 8ah 00 00000000 tl1 timer 1 low 8bh 00 00000000 tl2 ccu timer low cch 00 00000000 tmod timer 0 and 1 mode 89h t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 00 00000000 tor2h ccu reload register high cfh 00 00000000 tor2l ccu reload register low ceh 00 00000000 tpcr2h prescaler control register high cbh - - - - - - tpcr2h. 1 tpcr2h. 0 00 xxxxxx00 tpcr2l prescaler control register low cah tpcr2l. 7 tpcr2l. 6 tpcr2l. 5 tpcr2l. 4 tpcr2l. 3 tpcr2l. 2 tpcr2l. 1 tpcr2l. 0 00 00000000 trim internal oscillator trim register 96h - enclk trim.5 trim.4 trim.3 trim.2 trim.1 trim.0 [5] [6] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 11111111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 4: special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 17 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. functional description remark: please refer to the P89LPC932 users manual for a more detailed functional description. 8.1 enhanced cpu the P89LPC932 uses an enhanced 80c51 cpu which runs at 6 times the speed of standard 80c51 devices. a machine cycle consists of two cpu clock cycles, and most instructions execute in one or two machine cycles. 8.2 clocks 8.2.1 clock de?nitions the P89LPC932 device has several internal clocks as de?ned below: oscclk input to the divm clock divider. oscclk is selected from one of four clock sources (see figure 6 ) and can also be optionally divided to a slower frequency (see section 8.7 cpu clock (cclk) modi?cation: divm register ). note: f osc is de?ned as the oscclk frequency. cclk cpu clock; output of the clock divider. there are two cclk cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four cclk cycles). rcclk the internal 7.373 mhz rc oscillator output. pclk clock for the various peripheral devices and is cclk 2 . 8.2.2 cpu clock (oscclk) the P89LPC932 provides several user-selectable oscillator options in generating the cpu clock. this allows optimization for a range of needs from high precision to lowest possible cost. these options are con?gured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip rc oscillator, an oscillator using an external crystal, or an external clock source. the crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 khz to 12 mhz. 8.2.3 low speed oscillator option this option supports an external crystal in the range of 20 khz to 100 khz. ceramic resonators are also supported in this con?guration. 8.2.4 medium speed oscillator option this option supports an external crystal in the range of 100 khz to 4 mhz. ceramic resonators are also supported in this con?guration. 8.2.5 high speed oscillator option this option supports an external crystal in the range of 4 mhz to 12 mhz. ceramic resonators are also supported in this con?guration.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 18 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.2.6 clock output the P89LPC932 supports a user-selectable clock output function on the xtal2/clkout pin when crystal oscillator is not being used. this condition occurs if another clock source has been selected (on-chip rc oscillator, watchdog oscillator, external clock input on x1) and if the real-time clock is not using the crystal oscillator as its clock source. this allows external devices to synchronize to the P89LPC932. this output is enabled by the enclk bit in the trim register. the frequency of this clock output is 1 2 that of the cclk. if the clock output is not needed in idle mode, it may be turned off prior to entering idle, saving additional power. 8.3 on-chip rc oscillator option the P89LPC932 has a 6-bit trim register that can be used to tune the frequency of the rc oscillator. during reset, the trim value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 mhz, 2.5 %. end-user applications can write to the trim register to adjust the on-chip rc oscillator to other frequencies. 8.4 watchdog oscillator option the watchdog has a separate oscillator which has a frequency of 400 khz. this oscillator can be used to save power when a high clock frequency is not needed. 8.5 external clock input option in this con?guration, the processor clock is derived from an external source driving the xtal1/p3.1 pin. the rate may be from 0 hz up to 12 mhz. the xtal2/p3.0 pin may be used as a standard port pin or a clock output. fig 6. block diagram of oscillator control. ? 2 002aaa515 rtc cpu wdt divm cclk uart oscclk i 2 c pclk timer 0 and timer 1 high freq. med. freq. low freq. xtal1 xtal2 rc oscillator watchdog oscillator (7.3728 mhz 2.5%) (400 khz +20% -30%) pclk rcclk spi ccu 32 pll
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 19 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6 cpu clock (cclk) wake-up delay the P89LPC932 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. if the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 oscclk cycles plus 60 to 100 m s. if the clock source is either the internal rc oscillator, watchdog oscillator, or external clock, the delay is 224 oscclk cycles plus 60 to 100 m s. 8.7 cpu clock (cclk) modi?cation: divm register the oscclk frequency can be divided down up to 510 times by con?guring a dividing register, divm, to generate cclk. this feature makes it possible to temporarily run the cpu at a lower rate, reducing power consumption. by dividing the clock, the cpu can retain the ability to respond to events that would not exit idle mode by executing its normal program at a lower rate. this can also allow bypassing the oscillator start-up time in cases where power-down mode would otherwise be used. the value of divm may be changed by the program at any time without interrupting code execution. 8.8 low power select the P89LPC932 is designed to run at 12 mhz (cclk) maximum. however, if cclk is 8 mhz or slower, the clklp sfr bit (auxr1.7) can be set to 1 to lower the power consumption further. on any reset, clklp is 0 allowing highest performance access. this bit can then be set in software if cclk is running at 8 mhz or slower. 8.9 memory organization the various P89LPC932 memory spaces are as follows: ? data 128 bytes of internal data memory space (00h:7fh) accessed via direct or indirect addressing, using instructions other than movx and movc. all or part of the stack may be in this area. ? i data indirect data. 256 bytes of internal data memory space (00h:ffh) accessed via indirect addressing using instructions other than movx and movc. all or part of the stack may be in this area. this area includes the data area and the 128 bytes immediately above it. ? sfr special function registers. selected cpu registers and peripheral control and status registers, accessible only via direct addressing. ? x data external data or auxiliary ram. duplicates the classic 80c51 64 kb memory space addressed via the movx instruction using the sptr, r0, or r1. all or part of this space could be implemented on-chip. the P89LPC932 has 512 bytes of on-chip xdata memory. ? code 64 kb of code memory space, accessed as part of program execution and via the movc instruction. the P89LPC932 has 8 kb of on-chip code memory.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 20 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. the P89LPC932 also has 512 bytes of on-chip data eeprom that is accessed via sfrs (see section 8.26 data eeprom ). 8.10 data ram arrangement the 768 bytes of on-chip ram are organized as shown in ta b l e 5 . 8.11 interrupts the P89LPC932 uses a four priority level interrupt structure. this allows great ?exibility in controlling the handling of the many interrupt sources. the P89LPC932 supports 15 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port tx, serial port rx, combined serial port rx/tx, brownout detect, watchdog/real-time clock, i 2 c, keyboard, comparators 1 and 2, spi, ccu, data eeprom write completion. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers ien0 or ien1. the ien0 register also contains a global disable bit, ea, which disables all interrupts. each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers ip0, ip0h, ip1, and ip1h. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt source. if two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. if requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve pending requests of the same priority level. 8.11.1 external interrupt inputs the P89LPC932 has two external interrupt inputs as well as the keypad interrupt function. the two interrupt inputs are identical to those present on the standard 80c51 microcontrollers. these external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit it1 or it0 in register tcon. in edge-triggered mode, if successive samples of the intn pin show a high in one cycle and a low in the next cycle, the interrupt request ?ag ien in tcon is set, causing an interrupt request. table 5: on-chip data memory usages type data ram size (bytes) data memory that can be addressed directly and indirectly 128 idata memory that can be addressed indirectly 256 xdata auxiliary (external data) on-chip memory that is accessed using the movx instructions 512
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 21 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. if an external interrupt is enabled when the P89LPC932 is put into power-down or idle mode, the interrupt will cause the processor to wake-up and resume operation. refer to section 8.14 power reduction modes for details. (1) see section 8.18 capture/compare unit (ccu) fig 7. interrupt sources, interrupt enables, and power-down wake-up sources. 002aaa516 ie0 ex0 ie1 ex1 bopd ebo kbif ekbi interrupt to cpu wake-up (if in power-down) ewdrt cmf2 cmf1 ec ea (ie0.7) tf1 et1 ti & ri/ri es/esr ti est si ei2c spif espi rtcf ertc (rtccon.1) wdovf tf0 et0 any ccu interrupt (see note (1)) eccu eeif eief
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 22 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.12 i/o ports the P89LPC932 has four i/o ports: port 0, port 1, port 2, and port 3. ports 0, 1and 2 are 8-bit ports, and port 3 is a 2-bit port. the exact number of i/o pins available depends upon the clock and reset options chosen, as shown in ta b l e 6 . 8.12.1 port con?gurations all but three i/o port pins on the P89LPC932 may be con?gured by software to one of four types on a bit-by-bit basis. these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and input-only. two con?guration registers for each port select the output type for each port pin. p1.5 ( rst) can only be an input and cannot be con?gured. p1.2 (scl/t0) and p1.3 (sda/ int0) may only be con?gured to be either input-only or open-drain. 8.12.2 quasi-bidirectional output con?guration quasi-bidirectional output type can be used as both an input and output without the need to recon?gure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is driven low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. the P89LPC932 is a 3 v device, but the pins are 5 v-tolerant. in quasi-bidirectional mode, if a user applies 5 v on the pin, there will be a current ?owing from the pin to v dd , causing extra power consumption. therefore, applying 5 v in quasi-bidirectional mode is discouraged. a quasi-bidirectional port pin has a schmitt-triggered input that also has a glitch suppression circuit. 8.12.3 open-drain output con?guration the open-drain output con?guration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. to be used as a logic output, a port con?gured in this manner must have an external pull-up, typically a resistor tied to v dd . an open-drain port pin has a schmitt-triggered input that also has a glitch suppression circuit. table 6: number of i/o pins available clock source reset option number of i/o pins (28-pin package) on-chip oscillator or watchdog oscillator no external reset (except during power-up) 26 external rst pin supported 25 external clock input no external reset (except during power-up) 25 external rst pin supported 24 low/medium/high speed oscillator (external crystal or resonator) no external reset (except during power-up) 24 external rst pin supported 23
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 23 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.12.4 input-only con?guration the input-only port con?guration has no output drivers. it is a schmitt-triggered input that also has a glitch suppression circuit. 8.12.5 push-pull output con?guration the push-pull output con?guration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. a push-pull port pin has a schmitt-triggered input that also has a glitch suppression circuit. 8.12.6 port 0 analog functions the P89LPC932 incorporates two analog comparators. in order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. digital outputs are disabled by putting the port output into the input-only (high impedance) mode. digital inputs on port 0 may be disabled through the use of the pt0ad register, bits 1:5. on any reset, pt0ad[1:5] defaults to 0s to enable digital functions. 8.12.7 additional port features after power-up, all pins are in input-only mode. please note that this is different from the lpc76x series of devices. ? after power-up, all i/o pins except p1.5, may be con?gured by software. ? pin p1.5 is input only. pins p1.2 and p1.3 and are con?gurable for either input-only or open-drain. every output on the P89LPC932 has been designed to sink typical led drive current. however, there is a maximum total output current for all ports which must not be exceeded. please refer to table 8 dc electrical characteristics for detailed speci?cations. all ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. the slew rate is factory-set to approximately 10 ns rise and fall times. 8.13 power monitoring functions the P89LPC932 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. this is accomplished with two hardware functions: power-on detect and brownout detect. 8.13.1 brownout detection the brownout detect function determines if the power supply voltage drops below a certain level. the default operation is for a brownout detection to cause a processor reset, however it may alternatively be con?gured to generate an interrupt. brownout detection may be enabled or disabled in software.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 24 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. if brownout detection is enabled, the operating voltage range for v dd is 2.7 v to 3.6 v, and the brownout condition occurs when v dd falls below the brownout trip voltage, v bo (see table 8 dc electrical characteristics ), and is negated when v dd rises above v bo . if brownout detection is disabled, the operating voltage range for v dd is 2.4 v to 3.6 v. if the P89LPC932 device is to operate with a power supply that can be below 2.7 v, boe should be left in the unprogrammed state so that the device can operate at 2.4 v, otherwise continuous brownout reset may prevent the device from operating. for correct activation of brownout detect, the v dd rise and fall times must be observed. please see table 8 dc electrical characteristics for speci?cations. 8.13.2 power-on detection the power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. the pof ?ag in the rstsrc register is set to indicate an initial power-up condition. the pof ?ag will remain set until cleared by software. 8.14 power reduction modes the P89LPC932 supports three different power reduction modes. these modes are idle mode, power-down mode, and total power-down mode. 8.14.1 idle mode idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. any enabled interrupt source or reset may terminate idle mode. 8.14.2 power-down mode the power-down mode stops the oscillator in order to minimize power consumption. the P89LPC932 exits power-down mode via any reset, or certain interrupts. in power-down mode, the power supply voltage may be reduced to the ram keep-alive voltage v ram . this retains the ram contents at the point where power-down mode was entered. sfr contents are not guaranteed after v dd has been lowered to v ram , therefore it is highly recommended to wake up the processor via reset in this case. v dd must be raised to within the operating range before the power-down mode is exited. some chip functions continue to operate and draw power during power-down mode, increasing the total power used during power-down. these include: brownout detect, watchdog timer, comparators (note that comparators can be powered-down separately), and real-time clock (rtc)/system timer. the internal rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled. 8.14.3 total power-down mode this is the same as power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. the internal rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled. if the internal rc oscillator is used to clock
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 25 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. the rtc during power-down, there will be high power consumption. please use an external low frequency clock to achieve low power with the real-time clock running during power-down. 8.15 reset the p1.5/ rst pin can function as either an active-low reset input or as a digital input, p1.5. the rpe (reset pin enable) bit in ucfg1, when set to 1, enables the external reset input function on p1.5. when cleared, p1.5 may be used as an input pin. remark: during a power-up sequence, the rpe selection is overridden and this pin will always function as a reset input. an external circuit connected to this pin should not hold this pin low during a power-on sequence as this will keep the device in reset. after power-up this input will function either as an external reset input or as a digital input as de?ned by the rpe bit. only a power-up reset will temporarily override the selection de?ned by rpe bit. other sources of reset will not override the rpe bit. remark: during a power cycle, v dd must fall below v por (see table 8 dc electrical characteristics on page 45 ) before power is reapplied, in order to ensure a power-on reset. reset can be triggered from the following sources: ? external reset pin (during power-up or if user con?gured via ucfg1); ? power-on detect; ? brownout detect; ? watchdog timer; ? software reset; ? uart break character detect reset. for every reset source, there is a ?ag in the reset register, rstsrc. the user can read this register to determine the most recent reset source. these ?ag bits can be cleared in software by writing a 0 to the corresponding bit. more than one ?ag bit may be set: ? during a power-on reset, both pof and bof are set but the other ?ag bits are cleared. ? for any other reset, previously set ?ag bits that have not been cleared will remain set. 8.15.1 reset vector following reset, the P89LPC932 will fetch instructions from either address 0000h or the boot address. the boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00h. the boot address will be used if a uart break reset occurs, or the non-volatile boot status bit (boots tat.0) = 1, or the device is forced into isp mode during power-on (see P89LPC932 users manual ). otherwise, instructions will be fetched from address 0000h.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 26 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.16 timers/counters 0 and 1 the P89LPC932 has two general purpose counter/timers which are upward compatible with the standard 80c51 timer 0 and timer 1. both can be con?gured to operate either as timers or event counter. an option to automatically toggle the t0 and/or t1 pins upon timer over?ow has been added. in the timer function, the register is incremented every machine cycle. in the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled once during every machine cycle. timer 0 and timer 1 have ?ve operating modes (modes 0, 1, 2, 3 and 6). modes 0, 1, 2 and 6 are the same for both timers/counters. mode 3 is different. 8.16.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. in this mode, the timer register is con?gured as a 13-bit register. mode 0 operation is the same for timer 0 and timer 1. 8.16.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register are used. 8.16.3 mode 2 mode 2 con?gures the timer register as an 8-bit counter with automatic reload. mode 2 operation is the same for timer 0 and timer 1. 8.16.4 mode 3 when timer 1 is in mode 3 it is stopped. timer 0 in mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. when timer 1 is in mode 3 it can still be used by the serial port as a baud rate generator. 8.16.5 mode 6 in this mode, the corresponding timer can be changed to a pwm with a full period of 256 timer clocks. 8.16.6 timer over?ow toggle output timers 0 and 1 can be con?gured to automatically toggle a port output whenever a timer over?ow occurs. the same device pins that are used for the t0 and t1 count inputs are also used for the timer toggle outputs. the port outputs will be a logic 1 prior to the ?rst timer over?ow when this mode is turned on.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 27 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.17 real-time clock/system timer the P89LPC932 has a simple real-time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. the real-time clock can be a wake-up or an interrupt source. the real-time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. when it reaches all 0s, the counter will be reloaded again and the rtcf ?ag will be set. the clock source for this counter can be either the cpu clock (cclk) or the xtal oscillator, provided that the xtal oscillator is not being used as the cpu clock. if the xtal oscillator is used as the cpu clock, then the rtc will use cclk as its clock source. only power-on reset will reset the real-time clock and its associated sfrs to the default state. 8.18 capture/compare unit (ccu) this unit features: ? a 16-bit timer with 16-bit reload on over?ow. ? selectable clock, with prescaler to divide clock source by any integral number between 1 and 1024. ? 4 compare/pwm outputs with selectable polarity ? symmetrical/asymmetrical pwm selection ? 2 capture inputs with event counter and digital noise rejection ?lter ? 7 interrupts with common interrupt vector (one over?ow, 2 capture, 4 compare) ? safe 16-bit read/write via shadow registers. 8.18.1 ccu clock (ccuclk) the ccu runs on the ccuclk, which is either pclk in basic timer mode, or the output of a pll. the pll is designed to use a clock source between 0.5 mhz to 1 mhz that is multiplied by 32 to produce a ccuclk between 16 mhz and 32 mhz in pwm mode (asymmetrical or symmetrical). the pll contains a 4-bit divider to help divide pclk into a frequency between 0.5 mhz and 1 mhz. 8.18.2 ccu clock prescaling this ccuclk can further be divided down by a prescaler. the prescaler is implemented as a 10-bit free-running counter with programmable reload at over?ow. 8.18.3 basic timer operation the timer is a free-running up/down counter with a direction control bit. if the timer counting direction is changed while the counter is running, the count sequence will be reversed. the timer can be written or read at any time. when a reload occurs, the ccu timer over?ow interrupt flag will be set, and an interrupt generated if enabled. the 16-bit ccu timer may also be used as an 8-bit up/down timer.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 28 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.18.4 output compare there are four output compare channels a, b, c and d. each output compare channel needs to be enabled in order to operate and the user will have to set the associated i/o pin to the desired output mode to connect the pin. when the contents of the timer matches that of a capture compare control register, the timer output compare interrupt flag (tocfx) becomes set. an interrupt will occur if enabled. 8.18.5 input capture input capture is always enabled. each time a capture event occurs on one of the two input capture pins, the contents of the timer is transferred to the corresponding 16-bit input capture register. the capture event can be programmed to be either rising or falling edge triggered. a simple noise ?lter can be enabled on the input capture by enabling the input capture noise filter bit. if set, the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event. an event counter can be set to delay a capture by a number of capture events. 8.18.6 pwm operation pwm operation has two main modes, symmetrical and asymmetrical. in asymmetrical pwm operation the ccu timer operates in downcounting mode regardless of the direction control bit. in symmetrical mode, the timer counts up/down alternately. the main difference from basic timer operation is the operation of the compare module, which in pwm mode is used for pwm waveform generation. as with basic timer operation, when the pwm (compare) pins are connected to the compare logic, their logic state remains unchanged. however, since bit fco is used to hold the halt value, only a compare event can change the state of the pin. fig 8. asymmetrical pwm, downcounting. tor2 compare value timer value non-inverted inverted 0x0000 002aaa534
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 29 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.18.7 alternating output mode in asymmetrical mode, the user can set up pwm channels a/b and c/d as alternating pairs for bridge drive control. in this mode the output of these pwm channels are alternately gated on every counter cycle. 8.18.8 pll operation the pwm module features a phase locked loop that can be used to generate a ccuclk frequency between 16 mhz and 32 mhz. at this frequency the pwm module provides ultrasonic pwm frequency with 10-bit resolution provided that the crystal frequency is 1 mhz or higher. the pll is fed an input signal of 0.5 - 1 mhz and generates an output signal of 32 times the input frequency. this signal is used to clock the timer. the user will have to set a divider that scales pclk by a factor of 1-16. this divider is found in the sfr register tcr21. the pll frequency can be expressed as shown in equation 1 . (1) where: n is the value of plldv3:0. since n ranges in 0 - 15, the cclk frequency can be in the range of pclk to pclk 16 . fig 9. symmetrical pwm. tor2 compare value timer value non-inverted inverted 002aaa535 0 fig 10. alternate output mode. timer value 002aaa536 0 tor2 compare value a (or c) compare value b (or d) pwm output a (or c) (p2.6) pwm output b (or d) (p1.6) pll frequency plck n1 + () ------------------ =
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 30 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.18.9 ccu interrupts there are seven interrupt sources on the ccu which share a common interrupt vector. 8.19 uart the P89LPC932 has an enhanced uart that is compatible with the conventional 80c51 uart except that timer 2 over?ow cannot be used as a baud rate source. the P89LPC932 does include an independent baud rate generator. the baud rate can be selected from the oscillator (divided by a constant), timer 1 over?ow, or the independent baud rate generator. in addition to the baud rate generation, enhancements over the standard 80c51 uart include framing error detection, automatic address recognition, selectable double buffering and several interrupt options. the uart can be operated in 4 modes: shift register, 8-bit uart, 9-bit uart, and cpu clock/32 or cpu clock/16. 8.19.1 mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted or received, lsb ?rst. the baud rate is ?xed at 1 16 of the cpu clock frequency. fig 11. capture/compare unit interrupts. 002aaa537 interrupt to cpu toie2 (ticr2.7) toif2 (tifr2.7) ticie2a (ticr2.0) ticf2a (tifr2.0) ticie2b (ticr2.1) ticf2b (tifr2.1) tocie2a (ticr2.3) tocf2a (tifr2.3) tocie2b (ticr2.4) tocf2b (tifr2.4) tocie2c (ticr2.5) tocf2c (tifr2.5) tocie2d (ticr2.6) tocf2d (tifr2.6) ea (ien0.7) eccu (ien1.4) priority encoder other interrupt sources encint.0 encint.1 encint.2
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 31 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.19.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb ?rst), and a stop bit (logical 1). when data is received, the stop bit is stored in rb8 in special function register scon. the baud rate is variable and is determined by the timer 1 over?ow rate or the baud rate generator (described in section 8.19.5 baud rate generator and selection ). 8.19.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logical 0), 8 data bits (lsb ?rst), a programmable 9 th data bit, and a stop bit (logical 1). when data is transmitted, the 9 th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. when data is received, the 9 th data bit goes into rb8 in special function register scon, while the stop bit is not saved. the baud rate is programmable to either 1 16 or 1 32 of the cpu clock frequency, as determined by the smod1 bit in pcon. 8.19.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb ?rst), a programmable 9 th data bit, and a stop bit (logical 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 over?ow rate or the baud rate generator (described in section 8.19.5 baud rate generator and selection ). 8.19.5 baud rate generator and selection the P89LPC932 enhanced uart has an independent baud rate generator. the baud rate is determined by a baud-rate preprogrammed into the brgr1 and brgr0 sfrs which together form a 16-bit baud rate divisor value that works in a similar manner as timer 1. if the baud rate generator is used, timer 1 can be used for other timing functions. the uart can use either timer 1 or the baud rate generator output (see figure 12 ). note that timer t1 is further divided by 2 if the smod1 bit (pcon.7) is cleared. the independent baud rate generator uses oscclk. 8.19.6 framing error framing error is reported in the status register (sstat). in addition, if smod0 (pcon.6) is 1, framing errors can be made available in scon.7 respectively. if smod0 is 0, scon.7 is sm0. it is recommended that sm0 and sm1 (scon.7:6) are set up when smod0 is 0. fig 12. baud rate sources for uart (modes 1, 3). baud rate modes 1 and 3 sbrgs = 1 sbrgs = 0 smod1 = 0 smod1 = 1 ? 2 timer 1 overflow (pclk-based) baud rate generator (cclk-based) 002aaa419
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 32 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.19.7 break detect break detect is reported in the status register (sstat). a break is detected when 11 consecutive bits are sensed low. the break detect can be used to reset the device and force the device into isp mode. 8.19.8 double buffering the uart has a transmit double buffer that allows buffering of the next character to be written to sbuf while the ?rst character is being transmitted. double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. double buffering can be disabled. if disabled (dbmod, i.e., ss tat. 7 = 0), the uart is compatible with the conventional 80c51 uart. if enabled, the uart allows writing to snbuf while the previous data is being shifted out. double buffering is only allowed in modes 1, 2 and 3. when operated in mode 0, double buffering must be disabled (dbmod = 0). 8.19.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) unlike the conventional uart, in double buffering mode, the tx interrupt is generated when the double buffer is ready to receive new data. 8.19.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) if double buffering is disabled tb8 can be written before or after sbuf is written, as long as tb8 is updated some time before that bit is shifted out. tb8 must not be changed until the bit is shifted out, as indicated by the tx interrupt. if double buffering is enabled, tb8 must be updated before sbuf is written, as tb8 will be double-buffered together with sbuf data.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 33 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.20 i 2 c-bus serial interface i 2 c-bus uses two wires (sda and scl) to transfer information between devices connected to the bus, and it has the following features: ? bi-directional data transfer between masters and slaves ? multimaster bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus may be used for test and diagnostic purposes. a typical i 2 c-bus con?guration is shown in figure 13 . the P89LPC932 device provides a byte-oriented i 2 c-bus interface that supports data transfers up to 400 khz. fig 13. i 2 c-bus con?guration. other device with i 2 c-bus interface sda scl r p r p other device with i 2 c-bus interface p1.3/sda p1.2/scl P89LPC932 i 2 c-bus 002aaa559
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 34 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 14. i 2 c-bus serial interface block diagram. internal bus 002aaa421 address register comparator shift register 8 i2adr ack bit counter / arbitration & sync logic 8 i2dat timing & control logic serial clock generator cclk interrupt input filter output stage input filter output stage p1.3 p1.3/sda p1.2/scl p1.2 timer 1 overflow control registers & scl duty cycle registers i2con i2sclh i2scll 8 status decoder status bus status register 8 i2stat
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 35 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.21 serial peripheral interface (spi) the P89LPC932 provides another high-speed serial communication interfacethe spi interface. spi is a full-duplex, high-speed, synchronous communication bus with two operation modes: master mode and slave mode. up to 3 mbit/s can be supported in either master or slave mode. it has a transfer completion flag and write collision flag protection. the spi interface has four pins: spiclk, mosi, miso and ss: ? spiclk, mosi and miso are typically tied together between two or more spi devices. data ?ows from master to slave on mosi (master out slave in) pin and ?ows from slave to master on miso (master in slave out) pin. the spiclk signal is output in the master mode and is input in the slave mode. if the spi system is disabled, i.e., spen (spctl.6) = 0 (reset value), these pins are con?gured for port functions. ? ss is the optional slave select pin. in a typical con?guration, an spi master asserts one of its port pins to select one spi device as the current slave. an spi slave device uses its ss pin to determine whether it is selected. typical connections are shown in figures 16 through 18 . fig 15. spi block diagram. 002aaa497 cpu clock divider by 4, 16, 64, 128 select clock logic spi control register read data buffer 8-bit shift register spi control spi status register spr1 spif wcol spr0 spi clock (master) pin control logic s m s m m s miso p2.3 mosi p2.2 spiclk p2.5 ss p2.4 spi interrupt request internal data bus ssig spen spen mstr dord mstr cpha cpol spr1 spr0 mstr spen clock
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 36 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.21.1 typical spi con?gurations fig 16. spi single master single slave con?guration. fig 17. spi dual device con?guration, where either can be a master or a slave. 002aaa435 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port miso mosi spiclk ss 002aaa499 master slave 8-bit shift register spi clock generator spi clock generator 8-bit shift register miso mosi spiclk miso mosi spiclk ss ss
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 37 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 18. spi single master multiple slaves con?guration. 002aaa437 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port port miso mosi spiclk ss slave 8-bit shift register miso mosi spiclk ss
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 38 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.22 analog comparators two analog comparators are provided on the P89LPC932. input and output options allow use of the comparators in a number of different con?gurations. comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). otherwise the output is a zero. each comparator may be con?gured to cause an interrupt when the output value changes. the overall connections to both comparators are shown in figure 19 . the comparators function to v dd = 2.4 v. when each comparator is ?rst enabled, the comparator output and interrupt ?ag are not guaranteed to be stable for 10 microseconds. the corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt ?ag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. when a comparator is disabled the comparators output, cox, goes high. if the comparator output was low and then is disabled, the resulting transition of the comparator output from a low to high state will set the comparator ?ag, cmfx. this will cause an interrupt if the comparator interrupt is enabled. the user should therefore disable the comparator interrupt prior to disabling the comparator. additionally, the user should clear the comparator ?ag, cmfx, after disabling the comparator. 8.22.1 internal reference voltage an internal reference voltage generator may supply a default reference when a single comparator input pin is used. the value of the internal reference voltage, referred to as v ref , is 1.23 v 10%. fig 19. comparator input and output connections. comparator 1 cp1 cn1 (p0.4) cin1a (p0.3) cin1b (p0.5) cmpref v ref oe1 change detect co1 cmf1 interrupt 002aaa422 cmp1 (p0.6) ec change detect cmf2 comparator 2 oe2 co2 cmp2 (p0.0) cp2 cn2 (p0.2) cin2a (p0.1) cin2b
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 39 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.22.2 comparator interrupt each comparator has an interrupt ?ag contained in its con?guration register. this ?ag is set whenever the comparator output changes state. the ?ag may be polled by software or may be used to generate an interrupt. the two comparators use one common interrupt vector. if both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the ?ags to determine which comparator caused the interrupt. 8.22.3 comparators and power reduction modes either or both comparators may remain enabled when power-down or idle mode is activated, but both comparators are disabled automatically in total power-down mode. if a comparator interrupt is enabled (except in total power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. if the comparator output to a pin is enabled, the pin should be con?gured in the push-pull mode in order to obtain fast switching times while in power-down mode. the reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. comparators consume power in power-down and idle modes, as well as in the normal operating mode. this fact should be taken into account when system power consumption is an issue. to minimize power consumption, the user can disable the comparators via pcona.5, or put the device in total power-down mode. 8.23 keypad interrupt (kbi) the keypad interrupt function is intended primarily to allow a single interrupt to be generated when port 0 is equal to or not equal to a certain pattern. this function can be used for bus address recognition or keypad recognition. the user can con?gure the port via sfrs for different tasks. the keypad interrupt mask register (kbmask) is used to de?ne which input pins connected to port 0 can trigger the interrupt. the keypad pattern register (kbpatn) is used to de?ne a pattern that is compared to the value of port 0. the keypad interrupt flag (kbif) in the keypad interrupt control register (kbcon) is set when the condition is matched while the keypad interrupt function is active. an interrupt will be generated if enabled. the patn_sel bit in the keypad interrupt control register (kbcon) is used to de?ne equal or not-equal for the comparison. in order to use the keypad interrupt as an original kbi function like in 87lpc76x series, the user needs to set kbpatn = 0ffh and patn_sel = 1 (not equal), then any key connected to port 0 which is enabled by the kbmask register will cause the hardware to set kbif and generate an interrupt if it has been enabled. the interrupt may be used to wake up the cpu from idle or power-down modes. this feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. in order to set the ?ag and cause an interrupt, the pattern on port 0 must be held longer than 6 cclks.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 40 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.24 watchdog timer the watchdog timer causes a system reset when it under?ows as a result of a failure to feed the timer prior to the timer reaching its terminal count. it consists of a programmable 12-bit prescaler, and an 8-bit down counter. the down counter is decremented by a tap taken from the prescaler. the clock source for the prescaler is either the pclk or the nominal 400 khz watchdog oscillator. the watchdog timer can only be reset by a power-on reset. when the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. figure 20 shows the watchdog timer in watchdog mode. feeding the watchdog requires a two-byte sequence. if pclk is selected as the watchdog clock and the cpu is powered-down, the watchdog is disabled. the watchdog timer has a time-out period that ranges from a few m s to a few seconds. please refer to the P89LPC932 users manual for more details. 8.25 additional features 8.25.1 software reset the srst bit in auxr1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. care should be taken when writing to auxr1 to avoid accidental software resets. 8.25.2 dual data pointers the dual data pointers (dptr) provides two different data pointers to specify the address used with certain instructions. the dps bit in the auxr1 register selects one of the two data pointers. bit 2 of auxr1 is permanently wired as a logic 0 so that the dps bit may be toggled (thereby switching data pointers) simply by incrementing the auxr1 register, without the possibility of inadvertently altering other bits in the register. (1) watchdog reset can also be caused by an invalid feed sequence, or by writing to wdcon not immediately followed by a feed sequence. fig 20. watchdog timer in watchdog mode (wdte = 1). pre2 pre1 pre0 C C wdrun wdtof wdclk wdcon (a7h) control register prescaler 002aaa423 shadow register for wdcon 8-bit down counter wdl (c1h) watchdog oscillator pclk ? 32 mov wfeed1, #0a5h mov wfeed2, #05ah reset see note (1)
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 41 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.26 data eeprom the P89LPC932 has 512 bytes of on-chip data eeprom. the data eeprom is sfr based, byte readable, byte writable, and erasable (via row ?ll and sector ?ll). the user can read, write and ?ll the memory via sfrs and one interrupt. this data eeprom provides 100,000 minimum erase/program cycles for each byte. ? byte mode: in this mode, data can be read and written one byte at a time. ? row fill: in this mode, the addressed row (64 bytes) is ?lled with a single value. the entire row can be erased by writing 00h. ? sector fill: in this mode, all 512 bytes are ?lled with a single value. the entire sector can be erased by writing 00h. after the operation ?nishes, the hardware will set the eeif bit, which if enabled will generate an interrupt. the ?ag is cleared by software. 8.27 flash program memory 8.27.1 general description the P89LPC932 flash memory provides in-circuit electrical erasure and programming. the flash can be read, erased, or written as bytes. the sector and page erase functions can erase any flash sector (1 kb) or page (64 bytes). the chip erase operation will erase the entire program memory. in-system programming and standard parallel programming are both available. on-chip erase and write timing generation contribute to a user-friendly programming interface. the P89LPC932 flash reliably stores memory contents even after 10,000 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. the P89LPC932 uses v dd as the supply voltage to perform the program/erase algorithms. 8.27.2 features ? internal ?xed boot rom, containing low-level in-application programming (iap) routines ? user programs can call these routines to perform in-application programming (iap). ? default loader providing in-system programming via the serial port, located in upper end of user program memory. ? boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing ?exibility to the user. ? programming and erase over the full operating voltage range. ? read/programming/erase using isp/iap. ? any ?ash program/erase operation in 2 ms. ? parallel programming with industry-standard commercial programmers. ? programmable security for the code in the flash for each sector. ? 100,000 typical erase/program cycles for each byte. ? 10 year minimum data retention.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 42 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.27.3 isp and iap capabilities of the P89LPC932 flash organization: the P89LPC932 program memory consists of eight 1 kb sectors. each sector can be further divided into 64-byte pages. in addition to sector erase and page erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. an in-application programming (iap) interface is provided to allow the end users application to erase and reprogram the user code memory. in addition, erasing and reprogramming of user-programmable bytes including ucfg1, the boot status bit and the boot vector are supported. as shipped from the factory, the upper 512 bytes of user code space contains a serial in-system programming (isp) routine allowing for the device to be programmed in circuit through the serial port. flash programming and erasing: there are three methods of erasing or programming of the flash memory that may be used. first, the flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point. second, the on-chip isp boot loader may be invoked. this isp boot loader will, in turn, call low-level routines through the same common entry point that can be used by the end-user application. third, the flash may be programmed or erased using the parallel method by using a commercially available eprom programmer which supports this device. this device does not provide for direct veri?cation of code memory contents. instead, this device provides a 32-bit crc result on either a sector or the entire 8 kb of user code space. boot rom: when the microcontroller programs its own flash memory, all of the low-level details are handled by code that is contained in a boot rom that is separate from the flash memory. a user program simply calls the common entry point in the boot rom with appropriate parameters to accomplish the desired operation. the boot rom include operations such as erase sector, erase page, program page, crc, program security bit, etc. the boot rom occupies the program memory space at the top of the address space from ff00 to feff hex, thereby not con?icting with the user program memory space. power-on reset code execution: the P89LPC932 contains two special flash elements: the boot vector and the boot status bit. following reset, the P89LPC932 examines the contents of the boot status bit. if the boot status bit is set to zero, power-up execution starts at location 0000h, which is the normal start address of the users application code. when the boot status bit is set to a value other than zero, the contents of the boot vector is used as the high byte of the execution address and the low byte is set to 00h. the factory default setting is 01eh and corresponds to the address 1e00h for the default isp boot loader. this boot loader is pre-programmed at the factory into this address space and can be erased by the user. users who wish to use this loader should take precautions to avoid erasing the 1 kb sector from 1c00h to 1fffh. instead, the page erase function can be used to erase the eight 64-byte pages located from 1c00h to 1dffh. a custom boot loader can be written with the boot vector set to the custom boot loader, if desired. hardware activation of the boot loader: the boot loader can also be executed by forcing the device into isp mode during a power-on sequence (see the P89LPC932 users manual for speci?c information). this has the same effect as having a non-zero status byte. this allows an application to be built that will normally execute user code but can be manually forced into isp operation. if the factory default setting
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 43 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. for the boot vector (1eh) is changed, it will no longer point to the factory pre-programmed isp boot loader code. if this happens, the only way it is possible to change the contents of the boot vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the boot vector and boot status bit. after programming the flash, the status byte should be programmed to zero in order to allow execution of the users application code beginning at address 0000h. in-system programming (isp): in-system programming is performed without removing the microcontroller from the system. the in-system programming facility consists of a series of internal hardware resources coupled with internal ?rmware to facilitate remote programming of the P89LPC932 through the serial port. this ?rmware is provided by philips and embedded within each P89LPC932 device. the philips in-system programming facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses ?ve pins (v dd , v ss , txd, rxd, and rst). only a small connector needs to be available to interface your application to an external circuit in order to use this feature. in-application programming (iap): several in-application programming (iap) calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, con?guration bytes, and device identi?cation. all calls are made through a common interface, pgm_mtp. the programming functions are selected by setting up the microcontrollers registers before making a call to pgm_mtp at ff00h. 8.28 user con?guration bytes a number of user-con?gurable features of the P89LPC932 must be de?ned at power-up and therefore cannot be set by the program after start of execution. these features are con?gured through the use of the flash byte ucfg1. please see the P89LPC932 users manual for additional details. 8.29 user sector security bytes there are eight user sector security bytes, each corresponding to one sector. please see the P89LPC932 users manual for additional details.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 44 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. limiting values [1] stresses above those listed under table 7 limiting values may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in table 8 dc electrical characteristics and table 9 ac characteristics of this speci?cation are not implied. [2] this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated max imum. [3] parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. table 7: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit t amb(bias) operating bias ambient temperature - 55 +125 c t stg storage temperature range - 65 +150 c v xtal voltage on xtal1, xtal2 pin to v ss -v dd + 0.5 v v n voltage on any other pin (except xtal1, xtal2) to v ss - 0.5 +5.5 v i oh(i/o) high-level output current per i/o pin - 20 ma i ol(i/o) low-level output current per i/o pin - 20 ma i i/o(tot)(max) maximum total i/o current - 100 ma p tot(pack) total power dissipation per package based on package heat transfer, not device power consumption - 1.5 w
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 45 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. static characteristics table 8: dc electrical characteristics v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb =0 cto+70 c for commercial, - 40 cto+85 c for industrial, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit i dd power supply current, operating 3.6 v; 12 mhz [7] -1118ma i id power supply current, idle mode 3.6 v; 12 mhz [7] - 3.25 5 ma i pd power supply current, power-down mode, voltage comparators powered-down 3.6 v [7] - - m a i pd1 power supply current, total power-down mode 3.6 v [7] -15 m a v ddr v dd rise time - - 2 mv/ m s v ddf v dd fall time - - 50 mv/ m s v por power-on reset detect voltage - - 0.2 v v ram ram keep-alive voltage 1.5 - - v v th(hl) negative-going threshold voltage except scl, sda 0.22v dd 0.4v dd -v v il1 low-level input voltage scl, sda only - 0.5 - 0.3v dd v v th(lh) positive-going threshold voltage except scl, sda - 0.6v dd 0.7v dd v v ih1 high-level input voltage scl, sda only 0.7v dd - 5.5 v v hys hysteresis voltage port 1 - 0.2v dd -v v ol low-level output voltage, all ports, all modes except hi-z i ol = 20 ma; v dd = 2.4 v - 3.6 v [5] - 0.6 1.0 v i ol = 3.2 ma; v dd = 2.4 v - 3.6 v [5] - 0.2 0.3 v v oh high-level output voltage, all ports i oh = - 20 m a; v dd = 2.4 v - 3.6 v; quasi-bidirectional mode v dd - 0.3 v dd - 0.2 - v i oh = - 3.2 ma; v dd = 2.4 v - 3.6 v; push-pull mode v dd - 0.7 v dd - 0.4 - v i oh = - 20 ma; v dd = 2.4 v - 3.6 v; push-pull mode - - v c io input/output pin capacitance [6] - - 15 pf i il logical 0 input current, all ports v in = 0.4 v [4] -- - 80 m a i li input leakage current, all ports v in =v il or v ih [3] -- 10 m a i tl logical 1-to-0 transition current, all ports v in = 2.0 v at v dd = 3.6 v [2] - 30 - - 450 m a r rst internal reset pull-up resistor 10 - 30 k w v bo brownout trip voltage with bov = 1, bopd = 0 2.4 v < v dd < 3.6 v 2.40 - 2.70 v v ref bandgap reference voltage 1.11 1.23 1.34 v tc (vref) bandgap temperature coef?cient - 10 20 ppm/ c
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 46 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] typical ratings are not guaranteed. the values listed are at room temperature, 3 v. [2] port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. this curr ent is highest when v in is approximately 2 v. [3] measured with port in high-impedance mode. [4] measured with port in quasi-bidirectional mode. [5] see section 9 limiting values on page 44 for steady state (non-transient) limits on i ol or i oh . if i ol /i oh exceeds the test condition, v ol /v oh may exceed the related speci?cation. [6] pin capacitance is characterized but not tested. [7] the i dd , i id , and i pd speci?cations are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 47 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. dynamic characteristics table 9: ac characteristics t amb =0 cto+70 c for commercial, - 40 cto+85 c for industrial, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =12mhz unit min max min max f rcosc internal rc oscillator frequency 7.189 7.557 7.189 7.557 mhz f wdosc internal watchdog oscillator frequency 280 480 280 480 khz f osc oscillator frequency 0 12 - - mhz t clcl clock cycle see figure 22 83 - - - ns f clklp clklp active frequency 0 8 - - mhz glitch ?lter glitch rejection, p1.5/ rst pin - 50 - 50 ns signal acceptance, p1.5/ rst pin 125 - 125 - ns glitch rejection, any pin except p1.5/ rst - 15 - 15 ns signal acceptance, any pin except p1.5/ rst 50 - 50 - ns external clock t chcx high time see figure 22 33 t clcl - t clcx 33 - ns t clcx low time see figure 22 33 t clcl - t chcx 33 - ns t clch rise time see figure 22 -8 -8ns t chcl fall time see figure 22 -8 -8ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 21 16 t clcl - 1333 - ns t qvxh output data set-up to clock rising edge see figure 21 13 t clcl - 1083 - ns t xhqx output data hold after clock rising edge see figure 21 -t clcl + 20 - 103 ns t xhdx input data hold after clock rising edge see figure 21 -0 -0ns t dvxh input data valid to clock rising edge see figure 21 150 - 150 - ns spi interface f spi operating frequency 2.0 mhz (master) - - - - mhz 2.0 mhz (slave) 0 2.0 0 2.0 mhz 3.0 mhz (master) - - - - mhz 3.0 mhz (slave) 0 3.0 0 3.0 mhz t spicyc cycle time see figures 23 , 24 , 25 , 26 2.0 mhz (master) - - - - ns 2.0 mhz (slave) 500 - 500 - ns 3.0 mhz (master) - - - - ns 3.0 mhz (slave) 333 - 333 - ns
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 48 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz. t spilead enable lead time (slave) see figures 25 , 26 2.0 mhz 250 - 250 - ns 3.0 mhz 240 - 240 - ns t spilag enable lag time (slave) see figures 25 , 26 2.0 mhz 250 - 250 - ns 3.0 mhz 240 - 240 - ns t spiclkh spiclk high time see figures 23 , 24 , 25 , 26 master 340 - 340 - ns slave 190 - 190 - ns t spiclkl spiclk low time see figures 23 , 24 , 25 , 26 master 340 - 340 - ns slave 190 - 190 - ns t spidsu data set-up time (master or slave) see figures 23 , 24 , 25 , 26 100 - 100 - ns t spidh data hold time (master or slave) see figures 23 , 24 , 25 , 26 100 - 100 - ns t spia access time (slave) see figures 25 , 26 0 120 0 120 ns t spidis disable time (slave) see figures 25 , 26 2.0 mhz 0 240 - 240 ns 3.0 mhz 0 167 - 167 ns t spidv enable to output data valid see figures 23 , 24 , 25 , 26 2.0 mhz - 240 - 240 ns 3.0 mhz - 167 - 167 ns t spioh output data hold time see figures 23 , 24 , 25 , 26 0- 0-ns t spir rise time see figures 23 , 24 , 25 , 26 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns t spif fall time see figures 23 , 24 , 25 , 26 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns table 9: ac characteristics continued t amb =0 cto+70 c for commercial, - 40 cto+85 c for industrial, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =12mhz unit min max min max
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 49 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 21. shift register mode timing. 0 1234567 valid valid valid valid valid valid valid valid t xlxl 002aaa425 set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri fig 22. external clock timing. t chcl t clcx t chcx t c t clch 002aaa416 0.2 v dd + 0.9 0.2 v dd - 0.1 v v dd - 0.5 v 0.45 v fig 23. spi master timing (cpha = 0) t clcl t spiclkh t spiclkl master lsb/msb out master msb/lsb out t spidh t spidsu t spiclkl t spiclkh t spif t spioh t spidv t spir t spidv t spif t spif t spir t spir ss spiclk (cpol = 0) (output) 002aaa156 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 50 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 24. spi master timing (cpha = 1) t clcl t spiclkl t spiclkh master lsb/msb out master msb/lsb out t spidh t spidsu t spiclkh t spiclkl t spif t spioh t spidv t spidv t spir t spidv t spif t spir t spif t spir ss spiclk (cpol = 0) (output) 002aaa157 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 25. spi slave timing (cpha = 0) t clcl t spiclkh t spiclkl t spilead t spiclkh t spiclkl t spilag t spidsu t spidh t spidh t spidsu t spidsu t spir t spia t spioh t spioh t spidis t spir slave msb/lsb out msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spidv t spir t spif t spir t spif ss spiclk (cpol = 0) (input) 002aaa158 spiclk (cpol = 1) (input) miso (output) mosi (input) not defined
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 51 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 26. spi slave timing (cpha = 1) t clcl t spiclkh t spiclkl t spilead t spiclkh t spiclkl t spilag t spidsu t spidh t spidh t spidsu t spir t spia t spioh t spidis t spir slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spidv t spioh t spidv t spir t spif t spir t spif ss spiclk (cpol = 0) (input) 002aaa159 spiclk (cpol = 1) (input) miso (output) mosi (input) t spidsu table 10: ac characteristics, isp entry mode v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb =0 cto+70 c for commercial, - 40 cto+85 c for industrial, unless otherwise speci?ed. symbol parameter conditions min typ max unit t vr rst delay from v dd active 50 - - m s t rh rst high time 1 - 32 m s t rl rst low time 1 - - m s fig 27. isp entry waveform. 002aaa426 v dd rst t rl t vr t rh
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 52 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. comparator electrical characteristics [1] this parameter is characterized, but not tested in production. table 11: comparator electrical characteristics v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb =0 cto+70 c for commercial, - 40 cto+85 c for industrial, unless otherwise speci?ed. symbol parameter conditions min typ max unit v io offset voltage comparator inputs - - 20 mv v cr common mode range comparator inputs 0 - v dd - 0.3 v cmrr common mode rejection ratio [1] -- - 50 db response time - 250 500 ns comparator enable to output valid - - 10 m s i il input leakage current, comparator 0 < v in philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 53 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. package outline fig 28. plcc28 package outline (sot261-2). references outline version european projection issue date iec jedec jeita note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot261-2 112e08 ms-018 edr-7319 19 25 28 1 4 511 18 12 26 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k x y e e b d h e h v m b d z d a z e e v m a 0 5 10 mm scale 99-12-27 01-11-15 pin 1 index plcc28: plastic leaded chip carrier; 28 leads sot261-2 unit b mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 1.27 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) 11.58 11.43 12.57 12.32 2.16 0.81 0.66 1.22 1.07 0.180 0.165 0.02 0.12 0.25 0.01 0.05 0.085 0.007 0.004 0.007 1.44 1.02 0.057 0.040 0.456 0.450 11.58 11.43 0.456 0.450 0.495 0.485 12.57 12.32 0.495 0.485 10.92 9.91 0.43 0.39 10.92 9.91 0.43 0.39 0.085 0.032 0.026 0.048 0.042 e e inches d e a a 1 min. a 4 max. b p ey w v d (1) e (1) h d h e z d (1) max. z e (1) max. b 1 k a 3 l p e d e e
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 54 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 29. tssop28 package outline (sot361-1). unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot361-1 mo-153 99-12-27 03-02-19 0.25 w m b p z e 114 28 15 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 a max. 1.1
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 55 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 30. hvqfn28 package outline (sot788-1). 0.65 1 a 1 e h bc unit y e references outline version european projection issue date iec jedec jeita mm 6.1 5.9 6.1 5.9 d h 4.25 3.95 y 1 4.25 3.95 e 1 3.9 e 2 3.9 0.35 0.25 0.05 0.00 0.2 0.05 0.1 dimensions (mm are the original dimensions) sot788-1 mo-220 - - - - - - 0.75 0.50 l 0.1 v 0.05 w 0 2.5 5 mm scale sot788-1 hvqfn28: plastic thermal enhanced very thin quad flat package; no leads; 28 terminals; body 6 x 6 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 814 28 22 21 15 7 1 x d e c b a e 2 02-10-22 terminal 1 index area terminal 1 index area a c c b v m w m note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) e (1)
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 56 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 14.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 57 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 14.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 12: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core product data rev. 04 06 january 2004 58 of 60 9397 750 12379 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 15. revision history table 13: revision history rev date cpcn description 04 20040106 - product data (9397 750 12379); ecn 853-2433 01-a15016 dated 16 december 2003 modi?cations: ? table 4 special function registers : changed pleen to pllen. ? section 8.27.2 features on page 41 : adjusted bullet for erase/program cycles ? table 8 dc electrical characteristics on page 45 : adjusted value for i tl v in . 03 20031007 - product data (9397 750 12119); ecn 853-2433 30392 dated 30 september 2003 02 20030725 - product data (9397 750 11712); ecn 853-2433 30141 dated 23 july 2003. supersedes preliminary data P89LPC932_1 of 21 october 2002 (9397 750 10475)
9397 750 12379 philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 06 january 2004 59 of 60 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 16. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 18. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 19. licenses level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c speci?cation de?ned by philips. this speci?cation can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 06 january 2004 document order number: 9397 750 12379 contents philips semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80c51 core 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 special function registers . . . . . . . . . . . . . . . . 11 8 functional description . . . . . . . . . . . . . . . . . . 17 8.1 enhanced cpu . . . . . . . . . . . . . . . . . . . . . . . . 17 8.2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.3 on-chip rc oscillator option . . . . . . . . . . . . . . 18 8.4 watchdog oscillator option . . . . . . . . . . . . . . . 18 8.5 external clock input option . . . . . . . . . . . . . . . 18 8.6 cpu clock (cclk) wake-up delay . . . . . . . . . 19 8.7 cpu clock (cclk) modi?cation: divm register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8 low power select . . . . . . . . . . . . . . . . . . . . . . 19 8.9 memory organization . . . . . . . . . . . . . . . . . . . 19 8.10 data ram arrangement . . . . . . . . . . . . . . . . . 20 8.11 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.12 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.13 power monitoring functions. . . . . . . . . . . . . . . 23 8.14 power reduction modes . . . . . . . . . . . . . . . . . 24 8.15 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.16 timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 26 8.17 real-time clock/system timer. . . . . . . . . . . . . 27 8.18 capture/compare unit (ccu). . . . . . . . . . . . . 27 8.19 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.20 i 2 c-bus serial interface . . . . . . . . . . . . . . . . . . 33 8.21 serial peripheral interface (spi) . . . . . . . . . . . 35 8.22 analog comparators . . . . . . . . . . . . . . . . . . . . 38 8.23 keypad interrupt (kbi) . . . . . . . . . . . . . . . . . . 39 8.24 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 40 8.25 additional features . . . . . . . . . . . . . . . . . . . . . 40 8.26 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . 41 8.27 flash program memory. . . . . . . . . . . . . . . . . . 41 8.28 user con?guration bytes . . . . . . . . . . . . . . . . . 43 8.29 user sector security bytes . . . . . . . . . . . . . . . 43 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 44 10 static characteristics. . . . . . . . . . . . . . . . . . . . 45 11 dynamic characteristics . . . . . . . . . . . . . . . . . 47 12 comparator electrical characteristics . . . . . . 52 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 53 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 56 14.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 56 14.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 57 14.5 package related soldering information . . . . . . 57 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 58 16 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 59 17 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 18 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 19 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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